# STA – Setup and Hold Time Analysis

It is easy to get confused with the definitions of setup and hold violations. We are used to the definitions of setup and hold times for a single flipflop. The setup and hold violation checks done by STA tools are slightly different. PT aptly calls them max and min delay analysis. However, the other terminology is more common.

First a recap of the setup and hold time requirement of a flipflop.

Setup time is the minimum amount of time the data signal should be held steady before the clock event so that the data are reliably sampled by the clock. Hold time is the minimum amount of time the data signal should be held steady after the clock event so that the data are reliably sampled.

#### Setup Analysis (Max Delay Analysis)

Now, let us see what is meant by setup analysis for a timing path. Timing paths can be the following types:

1. Input port to a D pin of Flop.
2. CLK pin of Flop1 to D pin of Flop2
3. Q pin of flop to an output port
4. Input to output port through purely combinational logic.

We will take up a register to register path (2 above) for explanation.

Register to register path

We need to define some terms now. Consider the same clock goes to both FF1 & FF2. CLK is fed to both FF1&FF2. At clock edge A, FF1 is launching the data. That is, the D value causes a change in Q of FF1. So we call FF1 as lauching flop for this timing path. This signal will be captured at FF2 after one cycle.(For a single cycle path). So FF2 becomes our capturing flop, and clock edge B becomes our capturing edge.

Launch and Capture Edges

For ease of understanding, let us decide every component in the circuit is ideal. i.e. the flipflops have no setup and hold time requirements and clock is ideal. ie, CLK arrives at CP of FF1 & FF2 at 0 delay, edges coinciding.

The data path of the timing circuit is through CP of FF1 to D of FF2. Now let us calculate the delay encountered by data and clock while reaching FF2.

Data path delay
CLK->Q delay of FF1 + Comb path delay
In analysis, we call this the Arrival Time.

Clock path delay
0. (ideal clock)

However, we are checking the setup at the clock edge B. So we need to add one clock cycle to the clock path delay to get the Required Time.

Required Time = Clock period.

Data launched at FF1/CP should arrive at FF2/D in one clock period. So in setup check, we say a violation has occured if the data path delay is more than one clock cycle.

Now, let us increase the complication.

Clock has insertion delays. So the actual datapath delay is:
CLK delay till FF1/CP + CLK->Q delay of FF1 + Comb path delay

And the actual clock path delay is: CLK delay till FF2/CP.
Required Time = Clock period + CLK delay till FF2/CP.

Now, we should also take into account the setup requirement of FF2. ie. Data at FF2/D should be stable for at least TsFF2 before the clock edge. So the required time for data arrival at FF2/D is Clock period + CLK delay till FF2/CP- TsFF2 .If data arrives later than the clock path delay calculated above, the data won’t be captured at edge B.

From above, it is clear that setup analysis checks for the maximum allowable delay for the timing path.

Hold Analysis (Min Delay Analysis)

Now let us move on to Hold analysis.

Let us take the same timing path above. Here you are verifying that the data is not captured at FF2/D on launching edge A of the CLK. ie. it is checking for the minimum delay the data should take to arrive at the second flop for the circuit to function correctly.

Timing Analysis with ideal clock

ThFF2 is the library hold time value of flop FF2. If the Data launched by FF1 reaches D of FF2 fast enough, it may be captured at the same clock edge A by the flop FF2. Hence the minimum delay requirement for the timing path is that the path to D should at least take more time than the hold time requirement of the flop FF2, so as not to corrupt the data. (Look up the .lib file for the hold time values for pin D relative to clcok pin CP of the flip flop type of FF2).

In simple terms, this makes sure the launched data does not arrive at the capture point too soon. Data launched from launching flop is allowed to arrive at the input of the second flop only after a delay greater than its hold requirement so that it is properly captured.

With clock delays in place, data path delay is
CLK delay till FF1/CP + CLK->Q delay of FF1 + Comb path delay
Arrival time = CLK delay till FF1/CP + CLK->Q delay of FF1 + Comb path delay
Clock path delay is CLK delay till FF2/CP.
Required Time = CLK delay till FF2/CP + Hold requirement of FF2

Note that we are no longer adding the clock period to the required time. This is because the hold is checked with the same clock edge, and setup with the next clock edge.

From the figure above,assuming ideal clock, there is a window of time which is between the minimum required(ThFF2) and the maximum allowed(Clock period – TsFF2) that the timing path can correctly have. If the data path takes less time that ThFF2, we say a hold violation has occurred. If the data path takes more time than Clockperiod-TsFF2, we say a setup violation has occurred.

Take a timing report and draw the clock and data path diagrams to understand this further.

Sini is an expert on physical design flow and related methodologies. Outside work, she is an avid reader and generally loves being lazy.

## 22 comments on “STA – Setup and Hold Time Analysis”

1. Arpit Kapoor

arrival at FF2/D is Clock period + CLK delay till FF2/CP+ TsFF2 .If data arrives later than the clock path delay calculated above, the data wonâ€™t be captured at edge B.

This is to be corrected to Clock period + CLK delay till FF2/CP – TsFF2

2. krishna chaitanya

Can setup and hold violations possible for same path? if yes how can we resolve them?

1. Sini Mukundan Post author

1. You may see setup and hold violation on the same path for different corners.
2. If you are seeing setup and hold violation for the same path for same corner/view, you need to look at the report to see what’s happening. Most probably you have derates, uncertainties etc, and taken together with ‘slowest data+ fastest clock’ for setup check and ‘fastest data+ slowest clock’, it could report such a scenario. This is not valid in real life, so need to fix the constraints and analysis type.

3. sudha

Hey as already mentioned in one of the comments, data required time for setup should be Time period+ Clock Network delay of FF2/CP – Tsu.

4. plainspeak

Suppose there are two flops, A and B.
Suppose the signal C which is used as clock for flop B is also used as asynchronous Clr for flop A.
Will the synthesis tools ensure that the hold time for the following path is not violated?

C(Rise) -> flopA-Clr(Rise) -> flopA-Q(Fall) -> FlopB-D with respect to
C(Rise) -> FlopB-Clock

1. Sini Mukundan Post author

I suspect synthesis(and timing run in synthesis tool) won’t even consider this path. You can try adding this CLR pin as a sync pin and try to match the skew to clock pins, but I don’t know how effective that will be in ensuring you meet one cycle after the reset.

Of course, I am just theorizing. Maybe you can try out the report.

1. plainspeak

The clocks for flop A and clock to flop B come 100ns apart. So, the clocks being different to flops A and B won’t cause any timing issue. But, what I’m worried is the path I have mentioned in my previous message. Even I suspected that the path won’t be timed by the tools. I was reviewing a design which had the kind of logic described above and I found it odd. That’s why I asked your opinion. May be, I should try out synthesizing it and see if that path is timed.

5. charu

I am seeing setup violation from my block reg2out port to top-level reg2out port. There are no combinational logics between them. Should I add false path at these ports. If so, how?

1. Sini Mukundan Post author

Can you report the timing from the begin point of the block path to top level reg2out? Or is your block a hardmacro?

1. charu

My block is a hard macro and I am seeing atleast -1ns violation at the o/p port of my block to top level o/p port (violation is seen at reg2out path-group in top level) with no combinational logic in-between them. Is it related to incorrect budgeting?

6. salvinder

hi
could you please tell me why hold is checked on same edge of clock while setup on next edge? why hold is not responsible for deciding maxi frequency?

1. Sini Mukundan Post author

When you check hold, you are trying to make sure the minimum time required for the path is met. If the data reaches the capture flop too soon, it may not be stable enough. Hence the same clock edge.

max delay is what defines max frequency, whereas hold is min delay.

7. Trevor

“The data path of the timing circuit is through D of FF1 to CP of FF2. Now let us calculate the delay encountered by data and clock while reaching FF2.”

Shouldn’t the data path be from CP of FF1 to D of FF2?