There is the SDC command “set_clock_uncertainty” and there is the question of what clock uncertainty means.
The SDC manual states that `set_clock_uncertainty Specifies the uncertainty or skew characteristics of a single clock or between two different clocks. The timing analyzer uses this information to determine the worst possible clock arrival times for each timing check.`
Now why we need uncertainty values? For that let’s see various stages of digital design.
In synthesis, we assume the clock is ideal. There is no CTS yet, and clock pin of every sequential element is connected to the source clock without any buffering. Here the assumption is that each of these pins get clock at exactly the same time, without any variations. Since we know this isn’t going to be the case once implementation is completed, we want to specify some skew value to account for the actual delay variations between different sync points. This is not a real or measured value, but what we assume to be the worst skew once clock tree is built. The command set_clock_uncertainty lets you specify these numbers. The analyzer subtracts the setup uncertainty from the data required time for each applicable path, and adds the hold uncertainty to the data required time for each applicable path.
Let’s see an example.
set_clock_uncertainty -setup 0.5 [get_clocks SCLK] set_clock_uncertainty -hold 0.45 [get_clocks SCLK]
After specifying the above commands, setup and hold reports recalculate the clock path delay as follows. You can see that in the setup check, clock is faster due to uncertainty value, and in hold check, clock is slower.
Point Incr Path clock SCLK (rise edge) 200.00 200.00 clock network delay (ideal) 0.000 200.00 clock uncertainty -0.50 199.50
Point Incr Path clock SCLK (rise edge) 200.00 200.00 clock network delay (ideal) 0.00 200.00 clock uncertainty 0.45 200.45
Hence the set_clock_uncertainty command specifies a setup and hold margin for the synthesis tool for which the timing should be met, so as to account for actual variations in the clock.
Place & Route
Placement is done with an ideal clock and the reasons specified above are still valid for PnR tool, till placement. After CTS, you can propagate the clock and get the real skew numbers between clocks.So the uncertainty numbers as a means to specify skew is not valid anymore. However, you can still specify uncertainty as a design margin number. `set_clock_uncertainty -setup 0.5 [get_clocks SCLK]` in this context means that the worst slack without uncertainty should be > 0.5. i.e. every path in the design must meet timing with 0.5ns to spare. This is added typically to account for i)clock jitter ( The clock period is not constant. Some clock cycles are longer or shorter than others in a random fashion.See article on jitter.) and ii) on chip variation. See also set_timing_derate for another way to set the timing margins.