Multicycle paths between different clock domains

We have seen set_multicycle_path constraint for timing path within a single clock domain. Now let’s explore multicycle paths with two synchronous clock domains of different frequencies.

The SDC command `set_multicycle_path` has an option `-start/-end` that helps in these scenarios.

`set_multicycle_path [-setup|-hold] [-start|-end] -from -to path_multiplier`

-start indicates that multicycle information is relative to the startClock.
-end indicates that the multicycle information is relative to the endClock.
Default path_multiplier: Setup 1, Hold 0.
Setup: Regarding to EndClock by Default. (-end is the default)
Hold: Regarding to StartClock by Default. (-start is the default)

-start/-end options are relevant only for multifrequency paths.

Take the circuit below.

Here CLK1 and CLK2 are two different frequencies, and multicycle path needs to be set between FF1 & FF2.

CASE1: Slow launch clock and fast capture clock

Here, the red lines show the default setup and hold checking edges without any constraints specified. The setup is checked at edge 2 of CLK2. To move this one clock cycle of CLK2, specify
`set_multi_cycle_path 2 -setup -end -from FF1/CP -to FF2/D`

Once you set this, the hold check edge will also move to one clock cycle before the setup check, if you don’t specifically state the hold checking edge. (The green lines)

Now let’s try setting a hold constraint
`set_multi_cycle_path 1 -hold -start`

This is not the check we require. Let’s see what happens if we move the hold edge with respect to the capture clock.

This is the required constraint for a proper timing check. Move the hold edge ([ath_multiplier – 1) cycles from the endClock.

`set_multicycle_path 3 -setup -end
set_multicycle_path 2 -hold -end`

`set_multicycle_path 5 -setup -end
set_multicycle_path 4 -setup -end`

and so on.

CASE2: Fast launch clock and slow capture clock.

The above figure gives the default setup and hold check edges of a fast-to-slow timing path. This is equivalent to specifying
`set_multicycle_path 1 -setup -end -from FF1/CP -to FF2/D
set_multicycle_path 0 -hold -start -from FF1/CP -to FF2/D`

Now let’s constraint it for multicycle operation.

Here the setup check now has one extra clock cycle of the startClock. However, if you don’t specify any hold constraint, the hold check edge moves one clock cycle with respect to the setup check.

This correctly offsets the hold edge when the -setup is constrained with one extra clock cycle.


`set_multicycle_path 5 -setup -start -from FF1/CP -to FF2/D
set_multicycle_path 4 -hold -start -from FF1/CP -to FF2/D`

In conclusion, always constraint with respect to the high frequency clock.

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