Clock latency refers to the delay that is assumed to exist between the clock source and the flip-flop clock pin. This is typically used before layout, when clock is ideal. It is not the actual delay, but the delay specified by the user, to account for the clock network delay after implementation.
There are two terms associated with latency—Clock source latency is the time the clock signal takes to be propagated from its ideal waveform origin point to the clock definition point in the design. Network latency is the time the clock signal takes to be propagated from the clock definition point in the design to the clock pin of the sequential device.—The timing analyzer uses this information to determine clock arrival times in the absence of propagated clocking.
Once CTS is complete, the actual delay values to the clock sync points can be calculated. These are typically called insertion delays at this point. (Though some literature does use latency when defining skew as the “difference in best and worst latency”). In short, latency is the value we give the tool before CTS, and insertion delay is the actual value after CTS.
The command `set_clock_latency` Specifies explicitly the source latency or network latency of a clock. This command is typically used before layout, when propagated clocking cannot be used.
set_clock_latency 3.4 [get_clocks SCLK] `
In the timing report, the clock path will have the latency added as the clock network delay. The clock is ideal at this stage, but with a delay.
clock SCLK (rise edge) 200.00 200.00 clock network delay (ideal) 3.40 203.40
After CTS, use the command `set_propagated_clock` to use the real insertion delay values.
Also see set_clock_uncertainty command.