Clock Skew with NAND and NOR gates
i am doing my project in title ” NBTI induced clock skew reduction in clock trees” and i am referring IEEE paper ” Skew management of NBTI impacted gated clock trees”. I need to know how to reduce the clock skew, by using NAND and NOR gates. In this paper they mentioned NAND and NOR gate usage. Can u please give me a solution.